1. Field of the Invention
The present invention relates to a quasi-moving average circuit, more particularly relates to a circuit for computing a moving average value of data in digital signal processing.
When handling N number of sampling value series, which vigorously change in digital signal processing, to make their profile recognizable, values of bits of a shift register are added at an adder while sequentially shifting the sampling value series by a shift register and then the result is divided by N by a divider, thereby performing moving average computation for averaging for every certain number.
2. Description of the Related Art
As will be explained later with reference to the drawings, a conventional moving average circuit is constituted by a shift register which shifts an input data by N sampling values; a subtracter which subtracts the output data of the shift register from the input data; an accumulator which adds the output data of this subtracter and the data obtained by accumulation of the N times of samplings up to the preceding sampling; and a divider which divides the output data of this accumulator by N to generate output data.
In such a conventional moving average circuit, the above described shift register which stores the input data of the N samplings and further shifts the same is necessary. This shift register is generally constituted by a cascade-connection of N stages of flip-flops. Usually the above described N is selected to for example N=128, and therefore the circuit scale of the shift register becomes large. This is a problem.